1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a layout of power lines in a semiconductor memory device. More specifically, the present invention relates to an arrangement for driving sense amplifiers in a dynamic-type semiconductor memory device.
2. Description of the Background Art
A dynamic-type semiconductor memory device includes a memory cell composed of one MOS (insulated gate type field effect) transistor and one capacitor, and has a small area per bit accordingly. Such structural characteristics relatively readily realize a large storage capacity dynamic-type semiconductor memory device with high integration, high density, low cost per bit and a reduced chip area.
FIG. 1 is a schematic diagram of an entire arrangement of a conventional dynamic-type semiconductor memory device. With reference to FIG. 1, the dynamic-type semiconductor memory device includes a memory cell array 1 having a plurality of dynamic-type memory cells arranged in a matrix of rows and columns, an address buffer 2 for receiving external address signals A0-An and generating internal address signals, a row decoder 4 for decoding the internal address signals from the address buffer 2 and selecting a corresponding row of the memory cell array 1, a column decoder 5 for decoding the address signals from the address buffer 2 and generating a column selection signal for selecting a corresponding column of the memory cell array 1, a sense amp band 8 for sensing, amplifying, and latching information of memory cells connected to the row selected by the row decoder 4 of the memory cell array 1, and an I/0 gate 10 responsive to a column selection signal from the column decoder 6 for connecting a corresponding column of the memory cell array 1 to an internal data transmission line (I/O line).
The sense amp band 8 includes sense amplifiers provided corresponding to the respective columns of the memory cell array 1. Row address signals and column address signals are time-division-multiplexedly applied to the address buffer 2. The row decoder 4 decodes row address signals from the address buffer 2. The column decoder 6 decodes column address signals from the address buffer 2.
The dynamic-type semiconductor memory device further includes a control circuit 12 for receiving externally applied control clock signals, that is, a row address strobe signal RAS, a column address strobe signal CAS and a write enable signal WE to generate various internal control signals, a sense amp activation circuit 14 for generating signals for activating the sense amplifiers included in the sense amp band 8 in response to an internal control signal from the control circuit 12, and a sense amp drive circuit 16 for driving the sense amplifiers included in the sense amp band 8 in response to the sense amp activation signals from the sense amp activation circuit 14.
The signal RAS provides timing at which the address buffer 2 receives the external address signals A0-An as row address signals to generate internal row address signals, and also determines a memory cycle period of the dynamic-type semiconductor memory device.
The signal CAS provides timing at which the address buffer 2 receives the internal address signals A0-An as column address signals to generate internal column address signals. The signal WE determines the operation mode of the dynamic-type semiconductor memory device into a data writing operation mode or a data reading operation mode. The internal control signals from the control circuit 12 are applied to the address buffer 2, the row decoder 4 and the column decoder 6 and they are further applied to an input/output circuit 18.
The input/output circuit 18 communicates data with a selected memory cell in the memory cell array 1 through the I/O gate 10. The input/output circuit 18, in the data writing operation mode, receives external write data DQ to generate internal write data and transmits the internal write data to a selected memory cell through the internal data transmission line and the I/0 gate 10. In the data reading operation mode, the input/output circuit 18 generates external read data from the data of the selected memory cell, which data is transmitted to the internal data transmission line, through the I/O gate 10.
The sense amp activation circuit 14 generally delays the internal row address strobe signal RAS generated by the control circuit 12 by a predetermined time period to generate a sense amp activation signal. The sense amp drive circuit 15 drives sense amplifiers included in the sense amp band 8 in response to the sense amp activation signal. Operations of the sense amp drive circuit 16 and the sense amplifiers of the sense amp band 8 will be described in detail later.
The dynamic-type semiconductor memory device further includes an operation power supply potential line 22 connected to a power supply pad 20 for receiving an operation power supply potential Vcc and a ground line 26 connected to a ground pad 24 for receiving a ground potential Vss. The operation power supply potential line 22 and the ground line 26 for supplying a ground potential are both shown arranged to surround the memory device along a chip periphery. The arrangement of the power supply potential line 22 for supplying an operation power supply potential and the ground line 26 to surround the memory device aims an a stable supply of power supply voltages Vcc and Vss to an arbitrary position of the memory device through the power lines (including both of the power supply potential line and the ground line) 22 and 26 with a large width.
FIG. 2 is a diagram showing an arrangement of the memory cell array, the sense amp band and the sense amp driver circuit shown in FIG. 1. In FIG. 2, the memory cell array 1 includes a plurality of word lines WLs (only one of which is represented in FIG. 1) to each of which a row of memory cells MC is connected, and a plurality of pairs of bit lines BL and BL to each of which a column of memory cells MC is connected. A bit line BL and a complementary bit line BL are paired, to which data complementary to each other are transmitted. In a sensing operation, one of the bit line BL and the complementary bit line BL provides a reference potential to a potential of the other. The memory cell MC is arranged at a crossing between a word line WL and a bit line BL or BL. In other words, one memory cell MC is disposed at a crossing between a pair of bit lines and one word line.
Sense amplifiers SA included in the sense amp band 8 are disposed in parallel with a word line WL at one side of the memory cell array 1. The sense amplifier SA is arranged corresponding to each pair of bit lines BL and BL. All of the sense amplifiers SA included in the sense amp band 8 are connected through sense amp drive signal lines SP and SN. The reason why there are provided two separate signal lines of a sense amp drive signal line SP and a sense amp drive signal line SN is, as will be described in detail later, that the sense amplifier SA amplifies a potential on one bit line of a pair of bit lines BL and BL to an operation power supply potential Vcc level and amplifies the other bit line to a ground potential Vss level.
An equalize circuit EQ is provided for sense amp drive signals SP and SN in order to equalize the potentials thereof.
The sense amp drive circuit 16 connects the power supply potential line 24 and the ground line 26 arranged in parallel with bit lines BL and BL in proximity to the memory cell array 1 to sense amp drive signal lines SP and SN, respectively, in response to sense amp activation signals SO, SO and SOF. The sense amp drive circuit 16 includes a P channel MOS transistor P3 for connecting the sense amp drive signal line SP to the power supply potential line 24 in response to the sense amp activation signal SO, an N channel MOS transistor N3 for connecting the sense amp drive signal line SN to the ground line 26 in response to the sense amp activation signal SOF and an N channel MOS transistor N4 for connecting the sense amp drive signal line SN to the ground line 26 in response to the sense amp activation signal SO.
The N channel MOS transistor N3 has a relatively small current drivability, while the N channel MOS transistor N4 has a relatively large current drivability. First, the N channel MOS transistor N3 is turned on, so that the sense amp drive signal line SN is relatively slowly discharged to the ground potential Vss. Then, the N channel MOS transistor N4 is turned on, so that the sense amp drive signal line SN is discharged to the ground potential Vss at a high speed.
Such two-step drive of the sense amp drive signal line SN aims at improving sensitivity of sense amplifiers. In other words, the sense amp drive signal line SN is gradually discharged to the ground potential Vss level, the sense amplifier SA amplifies, to some extent, a potential difference between bit lines of each bit line pair and then the sense amp drive signal line SN is discharged to the ground potential Vss at a high speed. Thus, a sensing operation is performed at a high speed without reducing sensitivity of the sense amplifiers SA.
FIG. 3 is a diagram specifically showing an arrangement of the dynamic-type memory cell shown in FIG. 2. Shown as examples in FIG. 3 are a memory cell MC1 arranged an a crossing between a word line WL1 and a bit line BL and a memory cell MC2 arranged at a crossing between a word line WL2 and a complementary bit line BL. The memory cell MC1 includes a memory cell capacitor C1 for storing information in the form of electric charges, and a transfer gate MT1 comprising a N channel MOS transistor having a gate connected to the word line WL1, a source connected to the bit line BL and a drain connected to one electrode (storage node) of the memory capacitor C1. Similarly, the memory cell MC2 includes a memory capacitor C2 and a transfer gate MT2.
FIG. 4 is a diagram illustrating a specific arrangement of the sense amplifier SA shown in FIG. 2. In FIG. 4, the sense amplifier SA includes cross-coupled P channel MOS transistors P1 and P2 and cross-coupled N channel MOS transistors N1 and N2. The transistor P1 has a gate connected to the complementary bit line BL and a drain connected to the bit line BL. The transistor P2 has a gate connected to the bit line BL and a drain connected to the complementary bit line BL. Sources of the transistors P1 and P2 are in common connected to sense amp drive signal line SP.
The N channel MOS transistor N1 has a gate connected to the complementary bit line BL and a drain connected to the bit line BL. The transistor N2 has a gate connected to the bit line BL and a drain connected to the complementary bit line BL. Sources of the transistors N1 and N2 are in common connected to the sense amp drive signal line SN.
The transistors P1 and P2 constitute a P channel sense amplifier to amplify a higher potential of the potentials of the bit lines BL and BL to the operation power supply potential Vcc level. The N channel MOS transistors N1 and N2 constitute an N channel sense amplifier to amplify a lower potential of the potentials of the bit lines BL and BL to a ground potential Vss level.
FIG. 5 is a diagram illustrating an arrangement of the equalize circuit EQ shown in FIG. 2. The equalize circuit EQ includes an N channel MOS transistor N5 having a gate connected to receive an equalize signal EQS, a drain connected to the sense amp drive signal line SP and a source connected to the sense amp drive signal line SN, an N channel MOS transistor N6 having a drain connected to the sense amp drive signal line SN, a gate connected to receive the equalize signal EQS and a source coupled to receive a predetermined precharge potential VBL (normally at a level of Vcc/2), and an N channel MOS transistor N7 having a gate coupled to receive the equalize signal EQS, a source connected to the drive signal line SP and a drain connected to receive a precharge potential VBL. The transistor N5 short-circuits the drive signal lines SN and SP in response to the equalize signal EQS. The transistors N6 and N7 are turned on in response to the equalize signal EQS to maintain the drive signal lines SN and SP at a potential level of the precharge potential VBL.
Normally, a circuit having the same arrangement as that of the equalize circuit EQ shown in FIG. 5 is provided corresponding to a pair of bit lines BL and BL. The bit lines are precharged to a precharge potential of an intermediate potential of Vcc/2 level in a stand-by state. Operations of the circuits shown in FIGS. 2 to 5 will be described with reference to FIG. 6 which is an operation waveform diagram of these circuits.
When the signal RAS is at "H" (logical high), the memory device is in a stand-by state wherein the sense amp drive signal lines SP and SN are precharged to a predetermined precharge potential VBL and bit lines BL and BL are similarly precharged to an intermediate potential of Vcc/2.
When the signal RAS falls to "L" (logical low), a memory cycle starts. In response to the fall of the signal RAS, the address buffer 2 (see FIG. 1) generates an internal row address signals and applies the same to the row decoder 4. The row decoder 4 decodes the applied internal row address signals and selects a corresponding word line WL in the memory cell array 1 to bring a potential on the selected word line WL to "H".
In response to the rise of the potential on the selected word line WL, a transfer gate MT (a gate MT1 or MT2 in FIG. 3) in a memory cell connected to the selected word line is turned on. As a result, electric charges corresponding to storage information of the memory cell MC connected to the selected word line WL are moved between the cell MC and the bit lane BL (or BL). The movement of the electric charges changes a potential on the bit line BL or BL. In FIG. 6, the selected memory cell stores information "0", which causes a reduced potential on the bit line BL. No electric charge is moved for the other bit line (bit line BL in FIG. 6), whose potential in turn is at a predetermined precharge potential level. Herein, the respective bit lines BL and BL are released from a precharge/equalize state to assume a floating state in response to a fall of the signal RAS. This is also the case with the equalize circuit EQ provided at the sense amp drive signal lines SP and SN.
Then, the potential on the selected word line WL is increased and after a lapse of a predetermined time, the sense amp activation signal SOF first rises from "L" to "H", thereby turning on the transistor N3. As a result, the perennial of the sense amp drive signal line SN is gradually decreased from the precharge potential VBL to the ground potential Vss level. Responsively, the N channel sense amplifier in the sense amplifier SA operates to amplify a small potential difference between the bit lanes BL and BL. At this time, since the small potential difference between the bit lines BL and BL is gradually amplified, sensitivity of the sense amplifier SA is improved to accurately amplify the potential difference between the bit Lines BL and BL.
Then, after the potential difference between the bit lines BL and BL is amplified to some extent, the sense amp activation signal SO is brought to "H". As a result, the transistor N4 is turned on, so that the sense amp drive signal line SN is discharged to the ground potential Vss at a high speed. The transistor N4 causes the N channel sense amplifier in the sense amplifier SA to amplify a potential difference between the corresponding bit lines BL and BL at a high speed. Such two-step drive of the N channel sense amplifier enables discharge of a potential on a bit line having a lower potential out of the bit lines BL and BL to the ground potential level with high sensitivity and at a high speed.
Then, the sense amp activation signal SO is brought down to "L" from "H", and the sense amp drive signal line SP is connected to the power supply potential line 24 through the drive transistor P3. As a result, the P channel sense amplifiers included in the sense amplifier SA are activated to bring a bit line with a higher potential out of the bit lines BL and BL up to the power supply potential Vcc level (FIG. 6 shows a state wherein the complementary bit line BL is charged to "H", while the bit line BL is discharged to "L" level).
Then, the column address strobe signal CAS falls to "L", whereby the address buffer 2 generates internal column address signals. The column decoder 6 decodes the generated internal column address signals. At this time point, potentials on the bit lines BL and BL are stabilized to "L" and "H". As a result, a corresponding column is selected out of the memory cell array 1 and the selected column (that is, a bit line pair) is connected to the internal data transmission line. The signal WE determines which of data writing and data reading is to be performed. When the signal WE is at "H", data reading is to be performed, while when the signal WE is at "L", data writing is to be performed.
When the data writing or reading is performed, the dynamic-type semiconductor memory device returns to a stand-by state in preparation for a subsequent access cycle. In other words, the signals RAS and CAS sequentially rise to "H".
Responsively, the potential on the selected word line WL falls to "L", while the sense amp activation signals SO and SOF, and SO are returned to "L" and "H" of an inactive state. In parallel therewith, the equalize signal EQS rises to "H". The equalize circuit EQ is activated and the transistors N5, N6 and N7 (see FIG. 5) included in the equalize circuit EQ are all turned on. The sense amp drive signal lines SP and SN which have been at "H" and "L" levels are short-circuited to each other to attain an intermediate potential, Vcc/2.
At the same time, a precharge potential VBL (Vcc/2 level) generated by separate VBL generation circuit (not shown) is transmitted to the sense amp drive signal lines SP and SN through the transistors N6 and N7. As a result, the sense amp drive signal lines SN and SP are fixed to a precharge potential level to prepare for a subsequent sensing operation. The reason why the sense amp drive signal line is maintained at a precharge level of Vcc/2 is the same as that why the bit lines BL and BL are precharged to an intermediate potential, Vcc/2. That is, it is intended for reduction of power consumption and speed-up of a sensing operation.
With an increase in integration and a capacity of a dynamic-type semiconductor memory device, the nun%her of bit lines included in a memory cell array is increased and the number of sense amplifiers is accordingly increased. As a result, an increased number of sense amplifiers are connected to one sense amp drive signal line, and a length of the sense amp drive signal line is also increased. As a result, a resistance and a capacitance of the sense amp drive signal line are made larger.
In a conventional dynamic-type semiconductor memory device, each sense amplifier is connected to a power supply line (an operation power supply potential line and a ground line) arranged in parallel with a bit line on one side of a memory cell array through a sense amp drive circuit. Such arrangement causes a resistance and a capacitance of a sense amp drive signal line to give more effect on a sensing operation. Such problem will be described in the following.
Consideration is now given to potential changes of a node SN1 of the sense amp drive signal line located closest to the power supply lines 24 and 26 and a node SNn of the sense amp drive signal line SN farthest from the power supply Lines 24 and 26 as shown in FIG. 7. It is assumed that the sense amplifier SA of the node SN1 drives the bit line BL1, while the sense amplifier SA of the node SNn drives the bit line BLn.
When the sense amp activation signal SOF rises, the potential of node SN1 falls from the precharge level to the ground potential Vss level at a relatively high speed. On the other hand, the potential of the node SNn is gradually reduced by a resistance and a capacitance of the drive signal line SN. Therefore, a sensing operation of the bit line BL1 is carried out at a high speed, while a sensing operation of the bit line BLn is performed slowly.
Then, when the sense amp activation signal SO rises, the sense amp drive signal line SN is discharged to the ground potential Vss at a high speed. At the this time, the SN1 discharges electric charges of the bit line BL1 to the ground potential Vss at a high speed, while the node SNn gradually discharges electric charges of the bit line BLn due to the resistance and the capacitance of the drive signal line SN. A sensing operation of the bit line BLn therefore requires more time. An access time in data writing or reading is determined by the longest sensing operation time of the bit line BLn. As a result, an access time of the dynamic-type semiconductor memory device is increased.
Because of the resistance of the sense amp drive signal line SN, the drive signal line SN has a potential distribution, with a potential of the node SNn increased from the ground potential Vss by the potential VR. In this case, the discharged potential of the bit line BLn becomes higher than the ground potential Vss by a potential VR'. At this time, a P channel sense amplifier encounters the same problem, reducing a potential difference between bit lines BL and BL to disable stable data writing and reading.
Furthermore, an equalize circuit EQ is provided only at one end portion of each of the sense amp drive signal lines SN and SP. Therefore, while the equalize circuit EQ operates, a precharge potential VBL of the sense amp drive signal line SN is precharged to a potential VBL' lower than the desired intermediate potential Vcc/2 due to an interconnection resistance, which prevents an accurate sensing operation.
The problem illustrated in FIG. 7 similarly occurs to a P channel sense amplifier. Therefore, a conventional arrangement of an equalize circuit EQ and a sense amp drive circuit 16 provided only at one end portion of each of sense amp drive signal lines SP and SN can not ensure an accurate sensing operation as a capacity of a dynamic-type semiconductor memory device is increased.
In addition, in a conventional dynamic-type semiconductor memory device, a power supply line is located only along a periphery of a chip and a power supply potential required for each circuit is taken out of the power supply lines 24 and 26 proximate thereto through an interconnection. In this case, a desired power supply potential Vcc or Vss can not be obtained on a power supply line located farthest from the pads 20 and 24 (see FIG. 1), so that no accurate operation power supply potential or ground potential can be applied to each circuit. When the power supply potentials Vcc and Vss differ depending on a position in a semiconductor memory device, a signal potential varies according to a position in the device, which prevents an accurate operation.